• PinBall
• Parts
• PB-I01
• PB-I01.02

Protocol description

This protocol is used by the Input/Output control board to communicate with the different playfield components and other I/O subsystems in the pinball machine. The protocol follows a layered structure, which is explained in this document. The combination of physical specifications and logical protocol as defined herein is frequently referenced as PINCAN. This document PB-I01.02 specifies PINCAN version 1. All references without version numbering in this document refer to this version.

Physical layer

Electrical signaling

PINCAN operates on an asynchronous, serial bus system as defined in ISO 11898, commonly known as the Controller Area Network (CAN). The bus is operating at a speed of 500 kbit per second.

Mechanical connectors

Ribbon cable connector

Looking at the male connector from above (onto the pin side):

   9   7   5    3   1
+--------[   ]---------+
| IRQ 09V GND CANH GND |
| RST 09V GND CANL GND |
+----------------------+
   10  8   6    4   2

09V

Supply power, +9V regulated

CANH

CAN bus differential data, high side

CANL

CAN bus differential data, low side

GND

Supply ground

IRQ

Interrupt request

RST

Bus peripherals reset command

Cabling specification

Further details to be specified.

Message layer

Bus addressing

The extended address scheme is used, which gives 11 bit standard address plus 18 bit extended address range.

SID

Standard address ID bits

EID

Extended address ID bits

MC

Message class (3-bit, 0-7)

SA

Source address (8-bit, 0-255)

DA

Destination address (8-bit, 0-255)

R1

Reserved space 1 (2 bit), defined as 0

CH

Logical channel (3-bit, 0-7)

SD

Sub-device destination (5-bit, 0-31)

R2

Reserved space 2 (1 bit), defined as 0

Message classes

Device addresses

At least one numerical device address is assigned to each connected physical device on the bus. While the assignment of one device address is the default setup, complex devices may use more than one device address.

Additionally, there are special addresses defined, addressing, for example, all connected devices or all devices participating in a logical channel.

The device IDs from 0x08 upwards are available to bus devices.

D

Valid as message destination address

S

Valid as message source address

X

Valid as either source or destination address

R

Currently reserved for future use, valid neither as source nor as destination address

Logical channels

Logical channels provide a method of addressing multiple bus devices at once, with a single transmission. At the same time, a device not interested in any logical channel "multicast" traffic can easily filter out any traffic directed to such devices. Eight logical channels can be defined in a PINCAN environment, where one logical channel identificator (ranging from 0x01 to 0x07) is supposed to be statically assigned to one functional class of attached devices.

If the logical channel feature is not to be used for a message, the channel identification is set to 0x00.

Sub-device level addressing

If it is desired to address parts of one physical device connected to PINCAN, sub-device addresses can be assigned from 0x00 to 0x1f. If sub-device level addressing is not to be supported by a device, or a "base device" of a bus participant supporting sub-device addressing is to be assigned, address 0x00 is to be used for this purpose, and therefore does (in such devices) not represent a sub-device.

---

CategoryElectronics

---

THIS DATA IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS DATA, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

All product and brand names mentioned on there pages and in the source code are registered names and/or trademarks of the respective owner and are mentioned for identification purposes only.

For a full copyright notice, please see this link. For imprint and contact information, please see http://www.thiemo.net/.